The Do-It-Yourself Race Timer

How It Works

This description will make references to parts in the two lane version of the timer circuit. All other versions of the timer circuit follow the same basic design, but the parts may be labelled differently. If your timer was built from one of the other designs, use the pages of the two lane design to help identify the right parts in your circuit.

Turn your attention to Page 2 of the schematic diagram. IC3 is a 16.384 MHz crystal oscillator which supplies a stable time base for creating the other clock signals. The output of IC3 is frequency-divided in IC4 to produce a 1 KHz square wave. IC5 uses a pair of monostables to modify the width and phase of the 1 KHz square wave in order to produce a pair of clock signals that will drive the rest of the circuit.

Now turn your attention to Page 1 of the schematic diagram. S2 is a switch that is mechanically linked to the starting gate. When the starting gate is closed, the switch makes contact and energizes one leg of IC2a. The other leg remains de-energized until S3 is manually closed. When both legs are energized, the RESET signal is asserted. Note that S3 may be released at this time since D3 is now latching this input in the ON state.

Looking at Page 4, you will see two logic gates labelled IC13b and IC12b. They form a latch circuit. When reset to the ON state, this latch enables IC13a, which then passes the CLOCK1 signal to Q3. Q3 and Q4 switch on and off the current to the infrared LED labelled D10. D10 is mounted in the race track at the finish line, where it produces a pulsed beam of light spanning one lane of the track.

Page 3 shows the detector side of the circuit. Q1 is a phototransistor that is mounted at the finish line along with D10. Q1 senses the light coming from D10 and produces a current that varies with the intensity of the light. R11 converts the pulsed current into a voltage, which is then filtered through C7, R12, and R13 to eliminate low-frequency clutter. The operational amplifiers in IC6 compare the filtered voltage to a pair of reference voltages, and produce a high output when the filtered voltage is less than a threshold set by the reference voltages. D6 and D7 visually indicate threshold crossings to confirm that Q1 is receiving a good, strong signal.

If the optical path between D10 and Q1 is unobstructed, then IC6b will produce a high output every 1/1000 of a second. The monostable in IC7 and two D flipflops in IC8 together form a missing-pulse detector. If two sequential pulses are missing from the output of IC6b, then the BREAK1 signal is asserted, indicating that an object has broken the light beam at the finish line.

As long as the BREAK1 signal is not asserted, the latch circuit mentioned above remains in the ON state and keeps D10 flashing in time with the CLOCK1 signal. The latch circuit also enables the counting circuit in IC10 to count the pulses in the CLOCK1 signal, thereby measuring the elapsed time. However, the RESET signal continues to force the count to zero, so the counter does not advance.

Suddenly the starting gate on the race track opens, and the race begins. S2 breaks contact and one leg of IC2a de-energizes. The RESET signal is no longer asserted, so the counter in IC10 begins to advance in time with the CLOCK1 signal. When the racer in Lane 1 reaches the finish line, the light beam is blocked. Q1 no longer produces a current, so IC6b stops producing pulses. The missing-pulse detector asserts the BREAK1 signal. IC13b and IC12b latch in the OFF state and disable the counter in IC10. The counter stops advancing, and now displays the time elapsed for the racer in Lane 1.

Lane 2 uses IC13c, IC12c, D11, Q2, IC6d, IC7b, etc. in a similar fashion.

Copyright © 2001 Kristin Hammond

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